1. Field of the Invention
The present invention relates to an audio data synchronization format (sync format) detection circuit that can handle unknown new formats for digital audio by a minimum of software modifications.
Priority is claimed on Japanese Patent Application No. 2004-93995, filed Mar. 29, 2004, the content of which is incorporated herein by reference.
2. Description of Related Art
It is well-known that a sync format that indicates an audio standard, such as AC3, DTS, AAC, or the like, is attached at the head of digital audio data. FIG. 6 shows an example of a sync format. This figure shows the IEC 61937 sync format for AC3. As shown in the figure, the IEC 61937 sync format is stipulated to have six successive samples, where one sample is 48 bits. In addition, a configuration is used in which three samples that differ for each standard are added to the three common samples referred to as the IEC 61937 format.
FIG. 7 shows the IEC 60958 format, and this format is normally formed by two samples. In addition, a detection circuit that detects these sync formats is provided in the audio decoder.
Such kind of an audio signal processing apparatus that is equipped with a sync format detecting circuit is disclosed in Japanese Unexamined Patent Application, First Publication, No. 2003-76395.
Conventionally, when a new audio standard is created, naturally a sync format detecting circuit that detects the new format becomes necessary. Therefore, preferably a sync format detecting circuit that can handle future formats with minor modifications should be disposed in advance in the presently manufactured audio decoders as well.
It is possible to handle these new formats with only modifications of the software of the CPU (central processing unit). However, in this case, there is the problem that the CPU load becomes large. In addition, providing in advance hardware that assumes there will be new formats can be considered. However, in this case, the flexibility becomes small, and there are limits to handling unknown formats. When ample flexibility is provided, there are problems related to the enlargement of the hardware, such as an increase in the LSI chip area and an increase in the power consumption.